According to a related art, some semiconductor devices have a trench gate structure to control a current flowing between a source and a drain thereof. These semiconductor devices as a trench gate type transistor have a structure shown in FIG. 25. Here, FIG. 25 shows a top view of a substrate 4 on arrow XXV-XXV in FIG. 26A for clarity, i.e., FIG. 25 shows the top view of the substrate 4 with removing a layer-to-layer insulation film 11 from the device. As shown in FIG. 25, the semiconductor device has a cell region 87 including transistors and a gate lead wiring region 88 where a gate lead wiring pattern 18 is formed.
At the cell region 87, a plurality of trench gates is arranged in a net pattern with mesh structure. Each mesh, i.e., the form of the trench gate in the plan view is a quadrangle. The trench gate includes a trench 105. The trench 105 is formed in a surface layer of a semiconductor substrate 4 having an N− type of drift layer 2 and a P type base region 3, as shown in FIG. 26A. A gate oxide film 109 is formed to cover the inner wall of the trench 105, and a gate electrode 10 is formed in the trench with the gate oxide film 109. At both sides of the gate electrode 10, N+ type source regions 7 are formed in the surface layer of the semiconductor substrate 4, and a layer-to-layer insulation film 11 is formed on the gate electrode 10 and the N+ type source regions 7.
A plurality of trenches 114 extends from the cell region 87 to the gate lead wiring region 88, and terminates at a predetermined place in the gate lead wiring region 88. As shown in FIG. 26B, in the gate lead wiring region 88, a gate oxide film 115 is formed on the inner wall of the trench 114, and a gate electrode 16 is formed in the trench 114 with the gate oxide film 115.
The trench 114 is connected to one end of the trench 105 and extends perpendicularly from the end. For example, it is assumed that the semiconductor substrate 4 having a crystal plane of (001) of silicon (i.e., the (001) plane) is used. At the cell region 87, each side of the trench 105 is formed in a direction parallel to or perpendicular to a crystal axis <100> of silicon (i.e., the <100> axis). On the other hand, the trench 114 extends in a direction parallel to the <100> axis. That is, the sidewalls of both the trenches 105 and the trenches 114 are formed along the (100) plane and its equivalent planes such as a (010) plane, a ( 100) plane, and a (0 10) plane (i.e., the sidewalls have the (100)-oriented planes).
A gate lead wiring pattern 18 is formed on the gate oxide film 115, so that the gate electrode 16 is covered with the gate lead wiring pattern 18. Therefore, the gate electrodes 10, 16 and the gate lead wiring pattern 18 are electrically connected. Moreover, the gate electrodes 10, 16 are electrically connected to gate metal wires (not shown) through the gate lead wiring pattern 18.
As shown in FIG. 26B, a corner 116 is formed on the top surface of the gate electrode 16, so that the intensity of the electric field applied to the gate oxide film 115 at the corner becomes larger than that at other places. Accordingly, in the P type base region 3 which acting as the channel region of the transistor, the electric field intensity at the region close to the corner becomes higher than other portion. Then, this region turns on at a lower potential applied to the gate electrode. Therefore, this electric field concentration reduces the reliability of the gate electrode.
To increase in the reliability of the gate electrode structure, there may be a method to make the gate oxide film 115 thicker. However, in the process of forming the gate oxide films 109, 115, the gate oxide films 109, 115 are formed by thermal oxidation, and generally, the thermal oxidation is effected to the cell region 87 and the gate lead wiring region 88 at the same time. Accordingly, the thickness of the gate oxide film 109 at the cell region 87 would be also increased in accordance with increasing the thickness of the gate oxide film 115 at the gate lead wiring region 88.
If the gate oxide film 109 has a thicker portion at the cell region 87, this would reduce the mutual conductance, i.e., a response in current with respect to the gate potential becomes lower. Accordingly, the ON-resistance of the transistor would increase.